A DRAM performs a refresh operation periodically to restore data stored in a cell to maintain information stored in the cell. However, a number of word lines (row addresses) to be refreshed for a period refresh time is increased according to high integration of the DRAM, and a number of active sense amplifiers and bit lines is also increased. Therefore, the DRAM needs more current in the refresh operation than the normal operation. In this regard, techniques for achieving a high speed refresh operation and low power consumption have been suggested.
Referring to FIG. 1, a conventional refresh control circuit 100 includes an input buffer and command decoder 110, a row address latch circuit 120, a column address latch circuit 130, a row predecoder 140, a column predecoder 150, an internal address counter (refresh counter) 160, a row control circuit 170, a sense amplifier control unit 180, a row decoder 190, a column decoder 200, a sense amplifier 210 and a memory array 220. In the case of an SDRAM composed of four banks, one bank is enabled in the normal operation but the four banks are simultaneously enabled in the refresh operation. When the four banks are enabled at the same time, a large driving capacity is required to sense the bit lines. In addition, a cycle time of an external clock signal is shortened because of a high speed tendency of the DRAM. Accordingly, a RAS cycle time tRCmin (time consumed until all nodes of a core of the DRAM are electrically precharged by precharging a bit line sense amplifier and word lines) is gradually decreased. As a result, a cell having a poor sense amplifier driving capacity cannot restore data in a normal level during the refresh operation.
Referring to FIG. 2, sense amplifier driving signals SAP1 and SAN have a high level in delay time D1, and a sense amplifier driving signal SAP2 maintains a low level when a sense amplifier enable signal SAEN has a high level. A voltage level of a sense amplifier power supply node CSP is transmitted from VDD/2 level to a sense amplifier driving voltage Vcore1 (higher than Vcore2). After delay time D1, the sense amplifier driving signal SAP1 has a low level and the sense amplifier driving signal SAP2 has a high level. Therefore, the voltage level of the sense amplifier power supply node CSP becomes a sense amplifier driving voltage Vcore2 (lower than Vcore1). The sense amplifier 210 is operated during t1 period to sense the bit line. Thus, data stored in the memory cell are refreshed for a predetermined time t1.
However, according to the refresh property, the delay time D1 may be deficient for driving the sense amplifier 210 to the sense amplifier driving voltage Vcore1 level by using the sense amplifier driving signal SAP1. In this case, development of the bit line is abnormally slow in the cell. Thus, the word line is reset in a level lower than a desired level by ΔV. As a result, the cell having the poor refresh property fails to restore data in the refresh operation because of unsatisfactory refresh conditions.